dist_gen.sv

// Generated by SandPiper(TM) 1.1.1-2015/09/06-DEV for Redwood EDA internal use and partner use only (installed here: /home/steve/sp_eclipse_workspace/project/repo/distro).
// Redwood EDA claims no rights to this file and makes no claims as to its correctness.


`include "sandpiper_gen.vh"





//
// Scope: |calc
//

// For $aa.
logic aa_CALC_01H;

// For $aa_squared.
logic [31:0] aa_squared_CALC_01H;
logic [31:0] aa_squared_CALC_02H;

// For $bb.
logic bb_CALC_01H;

// For $bb_squared.
logic [31:0] bb_squared_CALC_01H;
logic [31:0] bb_squared_CALC_02H;

// For $cc.
logic [31:0] cc_CALC_03H;

// For $cc_squared.
logic [31:0] cc_squared_CALC_02H;
logic [31:0] cc_squared_CALC_03H;

// For $valid.
logic valid_CALC_01H;
logic valid_CALC_02H;
logic valid_CALC_03H;

// Clock signals.
logic Clk_valid_CALC_02H ;
logic Clk_valid_CALC_03H ;

//
// Scope: |none
//


generate



   //
   // Scope: |calc
   //


   // For $aa.

   // For $aa_squared.
   always_ff @(posedge Clk_valid_CALC_02H) aa_squared_CALC_02H[31:0] <= aa_squared_CALC_01H[31:0];

   // For $bb.

   // For $bb_squared.
   always_ff @(posedge Clk_valid_CALC_02H) bb_squared_CALC_02H[31:0] <= bb_squared_CALC_01H[31:0];

   // For $cc.

   // For $cc_squared.
   always_ff @(posedge Clk_valid_CALC_03H) cc_squared_CALC_03H[31:0] <= cc_squared_CALC_02H[31:0];

   // For $valid.
   always_ff @(posedge clk) valid_CALC_02H <= valid_CALC_01H;
   always_ff @(posedge clk) valid_CALC_03H <= valid_CALC_02H;



   //
   // Scope: |none
   //





endgenerate



//
// Gated clocks.
//

generate



   //
   // Scope: |calc
   //


   clk_gate gen_Clk_valid_CALC_02H(Clk_valid_CALC_02H, clk, 1'b1, (valid_CALC_01H ? 1'b1 : 1'bx), 1'b0);
   clk_gate gen_Clk_valid_CALC_03H(Clk_valid_CALC_03H, clk, 1'b1, (valid_CALC_02H ? 1'b1 : 1'bx), 1'b0);


   //
   // Scope: |none
   //





endgenerate



generate   // This is awkward, but we need to go into 'generate' context in the line that `includes the declarations file.
        

dist.tlv

\TLV_version 1a: tl-x.org
\SV
   // SystemVerilog module definition could go here.
   
\TLV  // enables TL-Verilog constructs
   |calc   // a pipeline, called "calc"
      ?$valid   // condition under which |calc transaction is valid
         
         // c = sqrt(a^2 + b^2), computed across 3 pipeline stages
         @1
            $aa_squared[31:0] = $aa * $aa;
            $bb_squared[31:0] = $bb * $bb;
         @2
            $cc_squared[31:0] = $aa_squared + $bb_squared;
         @3
            $cc[31:0] = sqrt($cc_squared);
        

dist.sv

`line 2 "dist.tlv" //_\TLV_version 1a: tl-x.org, generated by SandPiper(TM) 1.1.1-2015/09/06-DEV
`include "sp_default.vh" //_\SV
   // SystemVerilog module definition could go here.
   
`include "dist_gen.sv" //_\TLV  // enables TL-Verilog constructs
   //_|calc   // a pipeline, called "calc"
      //_?$valid   // condition under which |calc transaction is valid
         
         // c = sqrt(a^2 + b^2), computed across 3 pipeline stages
         //[email protected]
            assign aa_squared_CALC_01H[31:0] = `WHEN(valid_CALC_01H) aa_CALC_01H * aa_CALC_01H;
            assign bb_squared_CALC_01H[31:0] = `WHEN(valid_CALC_01H) bb_CALC_01H * bb_CALC_01H;
         //[email protected]
            assign cc_squared_CALC_02H[31:0] = `WHEN(valid_CALC_02H) aa_squared_CALC_02H + bb_squared_CALC_02H;
         //[email protected]
            assign cc_CALC_03H[31:0] = `WHEN(valid_CALC_03H) sqrt(cc_squared_CALC_03H); endgenerate
        
SandPiper